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Modern electronic warfare (EW) system designers are facing numerous challenges when attempting to develop effective solutions, including increased spectral congestion and more sophisticated surveillance techniques. Designers also are being pushed to reduce development times, driving them to employ custom hardware and firmware to achieve required levels of performance within system size, weight, and power constraints.

Fig. 1Fortunately, by properly applying high-speed data converters and fast digital signal processing components, such as field-programmable gate arrays (FPGAs), effective EW solutions are possible. To demonstrate, a reference design employing high-speed analog-to-digital converters (ADCs) from Analog Devices and FPGAs and channelization IP from Altera offers an effective solution for EW systems—one that enables fast time to market for EW and digital RF memory (DRFM) systems.

EW systems, which identify and counter electronic threats such as surveillance and tracking radar systems, are commonly categorized either as electronic support (ES), electronic attack (EA), or electronic protect (EP) systems. ES systems intercept and measure signal parameters to identify source and perform threat analysis. EA systems generate jamming signals to overpower the pulsed signals from a target radar.

Radar systems can also be “confused” by the use of a digital RF memory (DRFM), an integrated circuit or subsystem that can generate false radar return signals to deceive a radar. EP systems concentrate on processing and storing incoming signals to construct a signal database. This database is a continuously updated lookup table used to identify active radar systems.

Fig. 2Traditionally, these systems were developed on an analog electronic platform, but newer systems rely more on digital circuitry to take advantage of the signal-processing capabilities available in modern programmable logic devices (PLDs).

Threat detection from unknown targets in these systems requires a receiver which can operate over a wide frequency band to identify threat signals and initiate countermeasures. Typical EW systems may operate from DC to 20 GHz. In addition to wide-bandwidth requirements, practical EW systems should provide high dynamic range, high sensitivity, and accurate pulse characterization; new systems are being pushed to examine the bandwidths of interest faster with greater levels of detection sensitivity.

More complicated situations arise when incoming signals to an EW system arrive from numerous sources, each of which must be identified. Independent of intentional interference from adversaries, increased spectral congestion—particularly from the rapid expansion of communications infrastructure and the growth of wireless signals in the spectral environment— has made effective detection of threat signals even more challenging.

Demands for EW systems with smaller size, lighter weight, and lower power (SWaP) are making development cycles for new systems longer and more difficult. However, next-generation off-the-shelf solutions coupled with programmable building blocks are providing EW systems that can meet these difficult challenges. Two of the key building blocks critical for any EW system are the analog-to-digital converter (ADC) and real-time channelization intellectual property (IP). Both are instrumental in meeting the demands of new systems.

Fig. 3In many cases, the transition from analog to digital realms is a limited (limiting?) factor in ES, EA, and EP systems. A system designer is often faced with the tradeoffs of minimizing cost and system size, as well as achieving an optimal balance between the need to increase instantaneous surveillance bandwidth (so as to maximize the probability of intercept) and the requirement to minimize the effects of in-band high-power signals that can desensitize an EW system.

These requirements pose challenges in the design of an ADC, as well as in the design of the receiver front end that couples the signal content to the converter. Even if the ADC has excellent performance, the radio front end must be capable of preserving the signal quality, which results in a relentless push for high performance and low cost, as limits for high-speed ADCs in these EW systems.

Figure 1 shows a simple EW system. The key features of the system are the RF receiver, used for frequency downconversion and selection of the frequency band of interest for interrogation; the ADC(s) used to convert signals from the analog domain to digital form; and the digital signal-processing engine—typically an FPGA—configured to detect, determine, analyze, and manage the storage of signals of interest. DRFM and EA systems also include a corresponding transmission signal chain with a high-speed digital-to-analog converter (DAC) to return digital representations of EW signals back to analog form.

Historically, any increase in the instantaneous bandwidth of an EW receiver, while maintaining high system linearity, required either multiple overlapping receivers or an interleaved system architecture. Overlapped receivers each digitize a portion of the required bandwidth with digital signal processing that recombines the data contributions and observable spectrum from each channel.

Fig. 4An interleaved system architecture, in contrast, is often used with calibration to minimize the phase, offset, and gain differences between multiple data converters. Both EW receiver approaches are generally expensive to implement, with digital signal processing (DSP) often customized for optimum performance.

Newer high-speed sampling ADCs—such as the model AD9625 ADC from Analog Devices—represent solutions for next-generation EW systems, with increased instantaneous bandwidth and higher linearity for achieving optimum sensitivity levels. Model AD9625 is a 2.5-GSamples/s, 12-b ADC designed for high-bandwidth AC performance.1 It provides typical wideband signal-to-noise ratio (SNR), and spurious-free dynamic range (SFDR) of 57 and 80 dB, respectively, for a 1-GHz input bandwidth.

This ADC is also well suited for use in applications with multiple synchronized converters, which often is required to determine the signal angle of arrival (AoA). These converters also feature digital downconverters (DDC) to decimate and observe a smaller portion of the frequency spectrum on the output.

The AD9625 ADC can handle a small-signal analog bandwidth of more than 3 GHz,  providing a system designer with significant intermediate-frequency (IF) location flexibility. With first and second Nyquist sampling options and more than 1-GHz usable bandwidth, the ADC allows system designers to create front-end EW receiver architectures with optimal balance between filtering capabilities and system complexity.

This data converter is one of many signal-processing devices from Analog Devices that support both parallel and serial interfaces, including the JESD204B standard.2 Such interface capability is critical for supporting the high data rates and low-latency requirements of many EW systems.

To facilitate rapid prototyping and system developments, the AD9625 ADC is available as a VITA 42/FPGA mezzanine connector (FMC) card platform (Fig. 2). This platform provides reference designs showing how to optimize the signal conditioning prior to the ADC in a receiver design. This helps optimize performance and ensure that the data processing interfaces between the ADC and other signal processing units have sufficient bandwidth to support high-speed real-time data rates, at the same time using a practical commercial-off-the-shelf (COTS) receiver front-end architecture. The data converter enables an efficient architecture with 2.5-GSamples/s sampling rate and a high-speed conduit with minimum-sized footprint.

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